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dual high ip3, 700 mhz to 2800 mhz, double balanced, passive mixer, if amplifier, and wideband lo amplifier adl5812 rev. 0 information furnished by analog devices is believed to be accurate and reliable. however, no responsibility is assumed by analog devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. specifications subject to change without notice. no license is granted by implication or otherwise under any patent or patent rights of analog devices. trademarks and registered trademarks are the property of their respective owners. one technology way, p.o. box 9106, norwood, ma 02062-9106, u.s.a. tel: 781.329.4700 www.analog.com fax: 781.461.3113 ?2011 analog devices, inc. all rights reserved. features rf frequency: 700 mhz to 2800 mhz continuous lo frequency: 250 mhz to 2800 mhz, high-side or low-side inject if range: 30 mhz to 450 mhz power conversion gain of 6.7 db at 1900 mhz ssb noise figure of 11.6 db at 1900 mhz input ip3 of 27.2 dbm at 1900 mhz input p1db of 12.5 dbm at 1900 mhz typical lo drive of 0 dbm single-ended, 50 rf port single-ended or balanced lo input port single-supply operation: 3.6 v to 5.0 v serial port interface control on all functions exposed paddle 6 mm 6 mm, 40-lead lfcsp package applications multiband/multistandard cellular base station diversity receivers wideband radio link diversity downconverters multimode cellular extenders and broadband receivers functional block diagram rf1 vpif1 vpif2 serial port interface bias gen adl5812 rfct1 nc nc nc nc nc nc rfct2 rf2 v1lo1 nc nc nc loip loin le data clk v2lo1 ifgm1 nc ifop1 ifon1 nc ifgd1 v1lo 4 v1lo3 v1lo2 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 21 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 ifgm2 nc ifop2 ifon2 nc ifgd2 v 2lo4 v 2lo3 v 2lo2 09913-001 figure 1. general description the adl5812 uses revolutionary new broadband, square wave limiting, local oscillator (lo) amplifiers to achieve an unprecedented radio frequency (rf) bandwidth of 700 mhz to 2800 mhz. unlike conventional narrow-band sine wave lo amplifier solutions, this permits the lo to be applied either above or below the rf input over an extremely wide bandwidth. because energy storage elements are not used, the dc current consumption also decreases with decreasing lo frequency. the adl5812 uses highly linear, doubly balanced, passive mixer cores along with integrated rf and lo balancing circuits to allow single-ended operation. the adl5812 incorporates programmable rf baluns, allowing optimal performance over a 700 mhz to 2800 mhz rf input frequency. the balanced passive mixer arrangement provides outstanding lo-to-rf and lo-to-if leakages, excellent rf-to-if isolation, and excellent intermodulation performance over the full rf bandwidth. the balanced mixer cores also provide extremely high input linearity, allowing the device to be used in demanding wideband applications where in-band blocking signals may otherwise result in the degradation of dynamic range. blocker noise figure performance is comparable to narrow-band passive mixer designs. high linearity if buffer amplifiers follow the passive mixer cores, yielding typical power conversion gains of 6.7 db, and can be used with a wide range of output impedances. for low voltage applications, the adl5812 is capable of operation at voltages down to 3.6 v with substantially reduced current. two logic bits are provided to individually power down (1.5 ma for both channels) the two channels as desired. all features of the adl5812 are controlled via a 3-wire serial port interface, resulting in optimum performance and minimum external components. the adl5812 is fabricated using a bicmos high performance ic process. the device is available in a 40-lead, 6mm 6mm, lfcsp package and operates over a ?40c to +85c temperature range. an evaluation board is also available.
adl5812 rev. 0 | page 2 of 28 table of contents features .............................................................................................. 1 applications....................................................................................... 1 functional block diagram .............................................................. 1 general description ......................................................................... 1 revision history ............................................................................... 2 specifications..................................................................................... 3 timing characteristics ................................................................ 4 absolute maximum ratings............................................................ 5 esd caution.................................................................................. 5 pin configuration and function descriptions............................. 6 typical performance characteristics ............................................. 7 3.6 v performance...................................................................... 16 spurious performance................................................................ 17 circuit description......................................................................... 20 rf subsystem.............................................................................. 20 lo subsystem ............................................................................. 21 applications information .............................................................. 22 basic connections...................................................................... 22 if port .......................................................................................... 22 bias resistor selection ............................................................... 22 vgs programming..................................................................... 23 low-pass filter programming.................................................. 23 rf balun programming ............................................................ 23 register structure ........................................................................... 24 evaluation board ............................................................................ 25 outline dimensions ....................................................................... 27 ordering guide .......................................................................... 27 revision history 7/11revision 0: initial version
adl5812 rev. 0 | page 3 of 28 specifications v s = 5 v, t a = 25c, f rf = 1900 mhz, f lo = 1697 mhz, rf power = ?10 dbm, lo power = 0 dbm, r1 = r2 = 1200 , z o = 50 , optimum spi settings, unless otherwise noted. table 1. parameter test conditions/comments min typ max unit rf input interface return loss tunable to >20 db broadband via serial port 10 db input impedance 50 rf frequency range 700 2800 mhz output interface output impedance differential impedance, f = 200 mhz 260||1.2 ||pf if frequency range 30 450 mhz dc bias voltage 1 externally generated v s v lo interface lo power ?6 0 +10 dbm return loss 13.3 db input impedance 50 lo frequency range low-side or high-side lo 250 2800 mhz dynamic performance power conversion gain including 4:1 if port transformer and pcb loss 6.7 db voltage conversion gain z source = 50 , differential z load = 200 differential 13.1 db ssb noise figure 11.6 db ssb noise figure under blocking 5 dbm blocker present 10 mhz from wanted rf input, lo source filtered 21 db input third-order intercept f rf1 = 1900 mhz, f rf2 = 1901 mhz, f lo = 1697 mhz, each rf tone at ?10 dbm 27.2 dbm input second-order intercept f rf1 = 1900 mhz, f rf2 = 2000 mhz, f lo = 1697 mhz, each rf tone at ?10 dbm 55 dbm input 1 db compression point 12.5 dbm lo-to-if output leakage unfiltered if output ?37 dbm lo-to-rf input leakage ?46 dbm rf-to-if output isolation 26 db if/2 spurious ?10 dbm input power ?70 dbc if/3 spurious ?10 dbm input power ?78 dbc power interface supply voltage, v s 3.6 5 5.5 v quiescent current resistor programmable if current 412 ma power-down current 1.5 ma 1 supply voltage must be applied from external circuit through choke inductors.
adl5812 rev. 0 | page 4 of 28 timing characteristics low logic level 0.4 v, and high logic level 1.4 v. table 2. serial interface timing parameter limit unit test conditions/comments t 1 20 ns minimum le setup time t 2 10 ns minimum data-to-clk setup time t 3 10 ns minimum data-to-clk hold time t 4 25 ns minimum clk high duration t 5 25 ns minimum clk low duration t 6 10 ns minimum clk-to-le setup time t 7 20 ns minimum le pulse width timing diagram clk d a ta le db23 (msb) db22 db2 db1 (control bit c2) (control bit c3) db0 (lsb) (control bit c1) t 2 t 3 t 7 t 6 t 1 t 4 t 5 09913-002 figure 2. timing diagram
adl5812 rev. 0 | page 5 of 28 absolute maximum ratings table 3. parameter rating supply voltage, v pos 5.5 v clk, data, le 5.5 v if output bias 6.0 v rf input power 20 dbm lo input power 13 dbm internal power dissipation 2.5 w ja (exposed paddle soldered down) 30c maximum junction temperature 150c operating temperature range ?40c to +85c storage temperature range ?65c to +150c stresses above those listed under absolute maximum ratings may cause permanent damage to the device. this is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. exposure to absolute maximum rating conditions for extended periods may affect device reliability. esd caution
adl5812 rev. 0 | page 6 of 28 pin configuration and fu nction descriptions notes 1. nc = no connect. can be grounded. 2 . exposed pad must be connected to ground. rf1 vpif1 vpif2 rfct1 nc nc nc nc nc nc rfct2 rf2 v1lo1 nc nc nc loip loin le data clk v2lo1 ifgm1 nc ifop1 ifon1 nc ifgd1 v1lo 4 v1lo 3 v1lo 2 ifgm2 nc ifop2 ifon2 nc ifgd2 v2lo4 v2lo3 v2lo2 1 2 3 4 5 6 7 8 9 10 23 24 25 26 27 28 29 30 22 21 11 12 13 15 17 16 18 19 20 14 33 34 35 36 37 38 39 40 32 31 adl5812 top view (not to scale) 09913-003 figure 3. pin configuration table 4. pin function descriptions pin no. mnemonic description 1, 10 rf1, rf2 rf input. should be ac-coupled. 2, 9 rfct1, rfct2 rf balun center tap (ac ground). 3 to 8, 13, 16, 27 to 29, 35, 38 nc no connect. can be grounded. 11, 40 vpif1, vpif2 supply voltage for if amplifier. 12, 39 ifgm1, ifgm2 if amplifier bias control. 14, 15, 36, 37 ifop1, ifop2, ifon1, ifon2 differential open-collector if outputs. should be pulled up to v cc via external inductors. 17, 34 ifgd1, ifgd2 supply return for if amplifier. must be grounded. 18 to 21, 30 to 33 v1lo1, v1lo2, v1lo3, v1lo4, v2lo1, v2lo2, v2lo3, v2lo4 positive supply voltages for lo amplifiers. 22, 23, 24 clk, data, le serial port interface control. 25 loin ground return for lo input. must be ac coupled. 26 loip lo input. should be ac-coupled. epad exposed pad must be connected to ground.
adl5812 rev. 0 | page 7 of 28 typical performance characteristics v s = 5 v, t a = 25c, f rf = 1900 mhz, f lo = 1697 mhz, rf power = ?10 dbm, lo power = 0 dbm, r1 = r2 = 1200 , z o = 50 , optimum spi settings, unless otherwise noted. 250 300 350 400 450 200 700 900 1100 1300 1500 1700 1900 2100 2300 2500 2700 supply current (ma) rf frequency (mhz) t a = ?40c t a = +25c t a =+85c 09913-008 figure 4. supply current vs. rf frequency 0 1 2 3 4 5 6 7 8 9 10 11 12 700 900 1100 1300 1500 1700 1900 2100 2300 2500 2700 conversion gain (db) rf frequency (mhz) t a = ?40c t a = +25c t a =+85c 09913-011 figure 5. power conversion gain vs. rf frequency 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 700 900 1100 1300 1500 1700 1900 2100 2300 2500 2700 input ip3 (dbm) rf frequency (mhz) t a = ?40c t a = +25c t a =+85c 09913-019 figure 6 . input ip3 vs. rf frequency 30 35 40 45 50 55 60 65 70 700 900 1100 1300 1500 1700 1900 2100 2300 2500 2700 input ip2 (dbm) rf frequency (mhz) t a = ?40c t a = +25c t a =+85c 09913-016 figure 7 . input ip2 vs. rf frequency 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 700 900 1100 1300 1500 1700 1900 2100 2300 2500 2700 input p1db (dbm) rf frequency (mhz) t a =?40c t a = +25c t a =+85c 09913-020 figure 8. input p1db vs. rf frequency 6 7 8 9 10 11 12 13 14 15 16 700 900 1100 1300 1500 1700 1900 2100 2300 2500 2700 ssb noise figure (db) rf frequency (mhz) t a = ?40c t a = +25c t a = +85c 09913-025 figure 9. ssb noise figu re vs. rf frequency
adl5812 rev. 0 | page 8 of 28 250 300 350 400 450 200 ?40 ?20 0 20 40 60 80 supply current (ma) temperature (c) v pos = 4.75v v pos = 5.00v v pos = 5.25v 09913-026 figure 10 . supply current vs. temperature 5.0 5.5 6.0 6.5 7.0 7.5 8.0 ?40?200 20406080 conversion gain (db) temperature (c) v pos = 4.75v v pos = 5.00v v pos = 5.25v 09913-027 figure 11. power conversion gain vs. temperature 20 21 22 23 24 25 26 27 28 29 30 ?40?200 20406080 input ip3 (dbm) temperature (c) v pos = 4.75v v pos = 5.00v v pos = 5.25v 09913-028 figure 12. input ip3 vs. temperature ?40?200 20406080 temperature (c) 45 47 49 51 53 55 57 59 61 63 65 input ip2 (dbm) v pos = 4.75v v pos = 5.00v v pos = 5.25v 09913-029 figure 13. input ip2 vs. temperature ?40?200 20406080 temperature (c) 9 10 11 12 13 14 15 16 input p1db (dbm) v pos = 4.75v v pos = 5.00v v pos = 5.25v 09913-030 figure 14. input p1db vs. temperature ?40 ?20 0 20 40 60 80 temperature (c) 8 9 10 11 12 13 14 ssb noise figure (db) v pos = 4.75v v pos = 5.00v v pos = 5.25v 09913-031 figure 15. ssb noise figure vs. temperature
adl5812 rev. 0 | page 9 of 28 if frequency (mhz) 250 300 350 400 450 200 30 80 130 180 230 280 330 380 430 supply current (ma) rf = 900mhz rf = 1900mhz rf = 2500mhz 09913-032 figure 16. supply current vs. if frequency 0 1 2 3 4 5 6 7 8 conversion gain (db) rf = 900mhz rf = 1900mhz rf = 2500mhz 09913-033 if frequency (mhz) 30 80 130 180 230 280 330 380 430 9 10 figure 17 . power conversion gain vs. if frequency 15 17 19 21 23 25 27 29 31 33 35 input ip3 (dbm) rf = 900mhz rf = 1900mhz rf = 2500mhz 09913-034 if frequency (mhz) 30 80 130 180 230 280 330 380 430 figure 18 . input ip3 vs. if frequency 30 35 40 45 50 55 60 65 70 input ip2 (dbm) rf = 900mhz rf = 1900mhz rf = 2500mhz 09913-035 if frequency (mhz) 30 80 130 180 230 280 330 380 430 figure 19 . input ip2 vs. if frequency 0 2 4 6 8 10 12 14 16 input p1db (dbm) rf = 900mhz rf = 1900mhz rf = 2500mhz 09913-036 if frequency (mhz) 30 80 130 180 230 280 330 380 430 figure 20 . input p1db vs. if frequency 0 2 4 6 8 10 12 14 16 ssb noise figure (db) rf = 900mhz rf = 1900mhz rf = 2500mhz 09913-037 if frequency (mhz) 30 80 130 180 230 280 330 380 430 figure 21. ssb noise figure vs. if frequency
adl5812 rev. 0 | page 10 of 28 3 4 5 6 7 8 9 ?6 ?4 ?2 0 2 4 6 8 10 conversion gain (db) lo power (dbm) rf = 900mhz rf = 1900mhz rf = 2500mhz 09913-038 figure 22. power conversion gain vs. lo power ?6 ?4 ?2 0 2 4 6810 22 23 24 25 26 27 28 29 30 input ip3 (dbm) lo power (dbm) rf = 900mhz rf = 1900mhz rf = 2500mhz 09913-039 figure 23 . input ip3 vs. lo power ?6 ?4 ?2 0 2 4 6 8 10 35 40 45 50 55 60 65 70 75 input ip2 (dbm) lo power (dbm) rf = 900mhz rf = 1900mhz rf = 2500mhz 09913-040 figure 24 . input ip2 vs. lo power ?6 ?4 ?2 0 2 4 6 8 10 10 11 12 13 14 15 16 input p1db (dbm) lo power (dbm) rf = 900mhz rf = 1900mhz rf = 2500mhz 09913-041 figure 25. input p1db vs. lo power ?75 ?70 ?65 ?60 ?55 ?50 ?45 ? 40 700 900 1100 1300 1500 1700 1900 2100 2300 2500 2700 if/2 spurious (db) rf frequency (mhz) t a =?40c t a = +25c t a =+85c 09913-012 figure 26 . if/2 spurious vs. rf frequency, rf power = ?10 dbm ?90 ?85 ?80 ?75 ?70 ?65 ?60 ?55 ? 50 700 900 1100 1300 1500 1700 1900 2100 2300 2500 2700 if/3 spurious (db) rf frequency(mhz) t a = ?40c t a = +25c t a =+85c 09913-013 figure 27. if/3 spurious vs. rf frequency, rf power = ?10 dbm
adl5812 rev. 0 | page 11 of 28 percentage (%) 100 80 60 40 20 0 conversion gain (dbm) 7.4 7.2 7.6 7.8 7.0 mean: 7.37 sd: 0.12% 09913-065 figure 28. conversion gain distribution percentage (%) 100 80 60 40 20 0 input ip3 (dbm) 26 24 28 30 22 mean: 26.43 sd: 0.55% 09913-066 figure 29. input ip 3 distribution percentage (%) 100 80 60 40 20 0 input p1db (dbm) 11.8 11.3 12.3 12.8 10.8 mean: 11.82 sd: 0.30% 09913-064 figure 30. input p1db distribution 80 130 180 230 280 330 380 480430 30 100 200 300 400 0 500 2 4 6 8 0 10 if frequency (mhz) resistance ( ? ) capacitance (pf) 09913-057 rf = 900mhz rf = 1900mhz rf = 2500mhz figure 31. if output impedanc e (r parallel c equivalent) ?20 ?19 ?18 ?17 ?16 ?15 ?14 ?13 ?12 ?11 ?10 ?9 ?8 ?7 ?6 ? 5 700 900 1100 1300 1500 1700 1900 2100 2300 2500 2700 rf return loss (db) rf frequency (mhz) 09913-062 figure 32 . rf port return loss, fixed if ?20 ?19 ?18 ?17 ?16 ?15 ?14 ?13 ?12 ?11 ?10 ?9 ?8 ?7 ?6 ? 5 500 700 900 1100 1300 1500 1700 1900 2100 2300 2500 lo return loss (db) lo frequency (mhz) 09913-060 figure 33. lo return loss
adl5812 rev. 0 | page 12 of 28 ?35 ?30 ?25 ?20 ?15 ? 10 700 900 1100 1300 1500 1700 1900 2100 2300 2500 2700 rf frequency (mhz) rf-to-if isol a tion (db) 09913-023 t a =?40c t a = +25c t a =+85c figure 34 . rf-to-if isolation vs. rf frequency ?60 ?55 ?50 ?45 ?40 ?35 ?30 ?25 ?20 ?15 ? 10 500 700 900 1100 1300 1500 1700 1900 2100 2300 2500 lo frequency (mhz) lo-to-if leakage (dbm) t a =?40c t a = +25c t a =+85c 09913-021 figure 35 . lo-to-if leakage vs. lo frequency ?60 ?55 ?50 ?45 ?40 ?35 ?30 ?25 ?20 ?15 ? 10 500 700 900 1100 1300 1500 1700 1900 2100 2300 2500 lo frequency (mhz) lo-to-rf leakage (dbm) t a =?40c t a = +25c t a =+85c 09913-022 figure 36. lo-to-rf leakage vs. lo frequency ?55 ?50 ?45 ?40 ?35 ?30 ?25 ?20 ?15 ? 10 500 700 900 1100 1300 1500 1700 1900 2100 2300 2500 2 lo leakage (dbm) lo frequency (mhz) 09913-004 2 lo to rf 2 lo to if figure 37 . 2xlo leakage vs. lo frequency ?70 ?65 ?60 ?55 ?50 ?45 ?40 ?35 ?30 ?25 ?20 ?15 ? 10 500 700 900 1100 1300 1500 1700 1900 2100 2300 2500 3 lo leakage (dbm) lo frequency (mhz) 09913-005 3 lo to rf 3 lo to if figure 38. 3xlo leakage vs. lo frequency
adl5812 rev. 0 | page 13 of 28 4 6 8 10 12 14 16 700 900 1100 1300 1500 1700 1900 2100 2300 2500 2700 conversion gain and noise figure (db) rf frequency (mhz) gain noise figure vgs = 0 vgs = 1 vgs = 2 vgs = 3 vgs = 4 vgs = 5 vgs = 6 vgs = 7 09913-042 figure 39. power conversion gain and ssb noise figure vs. rf frequency for all vgs settings, rfb and lpf use optimum settings 700 900 1100 1300 1500 1700 1900 2100 2300 2500 2700 rf frequency (mhz) 0 5 10 15 20 25 30 input ip3 (dbm), input p1db (dbm) input ip3 input p1db vgs = 0 vgs = 1 vgs = 2 vgs = 3 vgs = 4 vgs = 5 vgs = 6 vgs = 7 09913-043 figure 40. input ip3 and input p1db vs . rf frequency for all vgs settings, rfb and lpf use optimum settings 0 5 10 15 20 25 30 ?30 ?25 ?20 ?15 ?10 ?5 0 5 10 noise figure (db) rf blocker level (dbm) rf = 956mhz rf = 1950mhz rf = 2583mhz 09913-061 figure 41. ssb noise figure vs. 10 mhz offset blocker level 500 600 700 800 900 1000 1100 1200 1300 1400 1500 1600 supply current (ma) if bias resistor value ( ? ) rf = 900mhz rf = 1900mhz rf = 2500mhz 09913-058 250 300 350 400 450 500 550 figure 42. supply current vs. if bias resistor value 0 3 6 9 12 15 18 21 24 27 30 2 4 6 8 10 12 14 16 18 20 22 500 600 700 800 900 1000 1100 1200 1300 1400 1500 1600 conversion gain (db) and noise figure (db) input ip3 if bias resistor value ( ? ) noise figure input ip3 gain 09913-059 rf = 900mhz rf = 1900mhz rf = 2500mhz figure 43. power conversion gain, noise figure, and input ip3 vs. if bias resistor value 0 10 20 30 40 50 60 70 700 900 1100 1300 1500 1700 1900 2100 2300 2500 2700 channel-to-channel isol a tion (db) rf frequency (mhz) t a =?40c t a = +25c t a =+85c 09913-006 figure 44. if channel-to-channel isolation vs. rf frequency
adl5812 rev. 0 | page 14 of 28 700 900 1100 1300 1500 1700 1900 2100 2300 2500 2700 rf frequency (mhz) rf frequency (mhz) 0 1 2 3 4 5 6 7 8 9 10 11 12 conversion gain (db) 09913-049 rfb = 0 rfb = 1 rfb = 2 rfb = 3 rfb = 4 rfb = 5 rfb = 6 rfb = 7 figure 45. conversion gain vs. rf frequency for all rfb settings, vgs and lpf use optimum settings 700 900 1100 1300 1500 1700 1900 2100 2300 2500 2700 rf frequency (mhz) rf frequency (mhz) input ip3 (dbm) 09913-050 rfb = 0 rfb = 1 rfb = 2 rfb = 3 rfb = 4 rfb = 5 rfb = 6 rfb = 7 20 21 22 23 24 25 26 27 28 29 30 figure 46. input ip3 vs. rf frequency for all rfb settings, vgs and lpf use optimum settings 700 900 1100 1300 1500 1700 1900 2100 2300 2500 2700 rf frequency (mhz) rf frequency (mhz) 5 6 7 8 9 10 11 12 13 14 15 16 17 input p1db (dbm) rfb = 0 rfb = 1 rfb = 2 rfb = 3 rfb = 4 rfb = 5 rfb = 6 rfb = 7 09913-051 figure 47. input p1db vs. rf frequency for all rfb settings, vgs and lpf use optimum settings 700 900 1100 1300 1500 1700 1900 2100 2300 2500 2700 rf frequency (mhz) rf frequency (mhz) 4 6 8 10 12 14 16 18 noise figure (db) rfb = 0 rfb = 1 rfb = 2 rfb = 3 rfb = 4 rfb = 5 rfb = 6 rfb = 7 09913-052 figure 48. noise figure vs. rf frequency for all rfb settings, vgs and lpf use optimum settings
adl5812 rev. 0 | page 15 of 28 700 900 1100 1300 1500 1700 1900 2100 2300 2500 2700 rf frequency (mhz) rf frequency (mhz) 0 1 2 3 4 5 6 7 8 9 10 conversion gain (db) lpf = 0 lpf = 1 lpf = 2 lpf = 3 09913-053 figure 49. conversion gain vs. rf frequency for all lpf settings, rfb and vgs use optimum settings 700 900 1100 1300 1500 1700 1900 2100 2300 2500 2700 rf frequency (mhz) rf frequency (mhz) 10 12 14 16 18 20 22 24 26 28 30 input ip3 (dbm) lpf = 0 lpf = 1 lpf = 2 lpf = 3 09913-054 figure 50. input ip3 vs. rf frequency for all lpf settings, rfb and vgs use optimum settings 0 2 4 6 8 10 12 14 16 input p1db (dbm) 700 900 1100 1300 1500 1700 1900 2100 2300 2500 2700 rf frequency (mhz) rf frequency (mhz) lpf = 0 lpf = 1 lpf = 2 lpf = 3 09913-055 figure 51. input p1db vs. rf frequency for all lpf settings, rfb and vgs use optimum settings 700 900 1100 1300 1500 1700 1900 2100 2300 2500 2700 rf frequency (mhz) rf frequency (mhz) 6 7 8 9 10 11 12 13 14 15 16 noise figure (db) lpf = 0 lpf = 1 lpf = 2 lpf = 3 09913-056 figure 52. noise figure vs. rf frequency for all lpf settings, rfb and vgs use optimum settings.
adl5812 rev. 0 | page 16 of 28 3.6 v performance v s = 5 v, t a = 25c, f rf = 1900 mhz, f lo = 1697 mhz, rf power = ?10 dbm, lo power = 0 dbm, r1 = r2 = 800 , z o = 50 , optimum spi settings, unless otherwise noted. 700 900 1100 1300 1500 1700 1900 2100 2300 2500 2700 rf frequency (mhz) 235 240 245 250 255 260 265 270 275 280 285 290 supply current (ma) rf frequency (mhz) t a = ?40c t a = +25c t a = +85c 09913-044 figure 53. supply current vs. rf frequency at 3.6 v 700 900 1100 1300 1500 1700 1900 2100 2300 2500 2700 rf frequency (mhz) rf frequency (mhz) 0 1 2 3 4 5 6 7 8 9 conversion gain (db) t a = ?40c t a = +25c t a = +85c 09913-045 figure 54. power conversion gain vs. rf frequency at 3.6 v 700 900 1100 1300 1500 1700 1900 2100 2300 2500 2700 rf frequency (mhz) rf frequency (mhz) 0 5 10 15 20 25 30 input ip3 (dbm) t a = ?40c t a = +25c t a = +85c 09913-046 figure 55. input ip3 vs. rf frequency at 3.6 v 700 900 1100 1300 1500 1700 1900 2100 2300 2500 2700 rf frequency (mhz) rf frequency (mhz) 0 10 20 30 40 50 60 70 input ip2 (dbm) t a = ?40c t a = +25c t a = +85c 09913-047 figure 56. input ip2 vs. rf frequency at 3.6 v 700 900 1100 1300 1500 1700 1900 2100 2300 2500 2700 rf frequency (mhz) rf frequency (mhz) 0 2 4 6 8 10 12 input p1db (dbm) - t a = ?40c t a = +25c t a = +85c 09913-048 figure 57. input p1db vs. rf frequency at 3.6 v 700 900 1100 1300 1500 1700 1900 2100 2300 2500 2700 noise figure (db) rf frequency (mhz) t a = ?40c t a = +25c t a = +85c 09913-063 0 2 4 6 8 10 12 14 16 18 20 22 24 figure 58. ssb noise figure vs. rf frequency at 3.6 v
adl5812 rev. 0 | page 17 of 28 spurious performance (n f rf ) ? (m f lo ) spur measurements were made using the standard evaluation board. mixer spurious products are measured in dbc from the if output power level. data was only measured fo r frequencies less than 6 ghz. typical noise floor of the measu rement system = ?100 dbm. 5 v performance v s = 5 v, t a = 25c, rf power = ?10 dbm, lo power = 0 dbm, r1 = r2 = 1200 , z o = 50 , optimum spi settings, unless otherwise noted. table 5. rf = 900 mhz, lo = 697 mhz m 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 0 ?38.6 ?19.2 ?37.5 ?22.2 ?48.1 ?42.0 ?63.0 ?59.2 1 ?30.4 0.0 ?36.3 ?19.2 ?52.5 ?41.5 ?60.6 ?53.8 ?78.7 ?64.8 2 ?60.9 ?54.1 ?78.0 ?54.1 ?67.2 ?77.8 ?76.1 ?97.7 ?91.5 adl5812 rev. 0 | page 18 of 28 table 7. rf = 2500 mhz, lo = 2297 mhz m 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 0 0 ?29.3 ?41.2 1 ?26.2 0.0 ?45.0 ?46.1 2 ?84.5 ?72.0 ?57.9 ?67.1 ?96.5 3 adl5812 rev. 0 | page 19 of 28 table 9. rf = 1900 mhz, lo = 1697 mhz m 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 0 ?32.6 ?29.0 ?60.9 1 ?34.0 0.0 ?53.6 ?56.6 ?86.3 2 ?72.9 ?72.4 ?82.0 ?73.1 ?76.8 adl5812 rev. 0 | page 20 of 28 circuit description the adl5812 consists of two primary components: the rf subsystem and the lo subsystem. the combination of design, process, and packaging technology allows the functions of these subsystems to be integrated into a single die, using mature packaging and interconnection technologies to provide a high performance device with excellent electrical, mechanical, and thermal properties. the wideband frequency response and flexible frequency programming simplifies the receiver design, saves on-board space, and minimizes the need for external components. the resulting balanced rf signal is applied to a passive mixer that commutates the rf input in accordance with the output of the lo subsystem. the passive mixer is essentially a balanced, low loss switch that adds minimum noise to the frequency translation. the only noise contribution from the mixer is due to the resistive loss of the switches, which is in the order of a few ohms. because the mixer is inherently broadband and bidirectional, it is necessary to properly terminate all idler (m n product) frequencies generated by the mixing process. terminating the mixer avoids the generation of unwanted intermodulation products and reduces the level of unwanted signals at the input of the if amplifier, where high peak signal levels can compromise the compression and intermodulation performance of the system. this termination is accomplished by the addition of a programmable low-pass filter network between the if amplifier and the mixer and in the feedback elements in the if amplifier. the rf subsystem consists of an integrated, tunable, low loss rf balun; a double balanced, passive mosfet mixer; a tunable sum termination network; and an if amplifier. the lo subsystem consists of a multistage limiting lo amplifier. the purpose of the lo subsystem is to provide a large, fixed amplitude, balanced signal to drive the mixer independent of the level of the lo input. a block diagram of the device is shown in figure 59 . the if amplifier is a balanced feedback design that simultaneously provides the desired gain, noise figure, and input impedance that is required to achieve the overall performance. the balanced open-collector output of the if amplifier, with an impedance modified by the feedback within the amplifier, permits the output to be connected directly to a high impedance filter, a differential amplifier, or an analog-to-digital converter (adc) input while providing optimum second-order intermodulation suppression. the differential output impedance of the if amplifier is approximately 200 . if operation in a 50 system is desired, the output can be transformed to 50 by using a 4:1 transformer or an lc impedance matching network. rf1 vpif1 vpif2 serial port interface bias gen adl5812 rfct1 nc nc nc nc nc nc rfct2 rf2 v1lo1 nc nc nc loip loin le data clk v2lo1 ifgm1 nc ifop1 ifon1 nc ifgd1 v1lo 4 v1lo3 v1lo2 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 21 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 ifgm2 nc ifop2 ifon2 nc ifgd2 v2lo4 v2lo3 v2lo2 09913-067 the intermodulation performance of the design is generally limited by the if amplifier. the ip3 performance can be optimized by adjusting the low-pass filter between the mixer and the if amplifier. further optimization can be made by adjusting the if current with an external resistor. figure 42 and figure 43 illustrate how various if resistors affect the performance with a 5 v supply. additionally, dc current can be saved by increasing the if resistor. it is permissible to reduce the if amplifiers dc supply voltage to as low as 3.3 v, further reducing the dissipated power of the part. (note that no performance enhancement is obtained by reducing the value of these resistors, and excessive dc power dissipation may result.) figure 59. simpli fied schematic rf subsystem the single-ended, 50 rf input is internally transformed to a balanced signal using a tunable, low loss, unbalanced-to-balanced (balun) transformer. this transformer is made possible by an extremely low loss metal stack, which provides both excellent balance and dc isolation for the rf port. although the port can be dc connected, it is recommended that a blocking capacitor be used to avoid running excessive dc current through the part. the rf balun can easily support an rf input frequency range of 700 mhz to 2800 mhz. this balun is tuned over the frequency range by spi controlled switched capacitor networks at the input and output of the rf balun. because the mixer is bidirectional, the tuning of the rf and if ports is linked, and it is possible for the user to optimize gain, noise figure, ip3, and impedance match via the spi. this feature permits high performance operation and is achieved entirely using spi control. additionally, the performance of the mixer can be improved by setting the optimum gate voltage on the passive mixer, which is also controlled by the spi to enable optimum performance of the part. see the applications information section for examples of this tuning.
adl5812 rev. 0 | page 21 of 28 lo subsystem the lo amplifier is designed to provide a large signal level to the mixer to obtain optimum intermodulation and compression performance. the resulting lo amplifier provides very high performance over a wide range of lo input frequencies. the ideal waveshape for switching the passive mixer is a square wave at the lo frequency to cause the mixer to switch through its resistive region (from on to off and off to on) as rapidly as possible. while it has always been possible to generate such a square wave, the amount of dc current required to generate a large amplitude square wave at high frequencies has made it impractical to create such a mixer. novel circuitry within the adl5812 permits the generation of a near-square wave output at frequencies up to 2800 mhz with dc current that compares favorably with that employed by narrow-band passive mixers. the input stages of the lo amplifier provide common-mode rejection, permitting the lo input to be driven either single ended or balanced. for a single-ended input, either loip or loin can be grounded. it is desirable to dc block the lo inputs to avoid damaging the part by the accidental application of a large dc voltage to the part. in addition, the lo inputs are internally dc blocked. because the lo amplifier is inherently wideband, the adl5812 can be driven with either high-side or low-side lo by simply setting the optimum rf balun and lpf inputs to the spi. the lo amplifier converts a variable level, single or balanced input signal (?6 dbm to +10 dbm) to a hard voltage limited, balanced signal internally to drive the mixer. excellent performance can be obtained with a 0 dbm input level; however, the circuit continues to function at considerably lower levels of lo input power. the performance of this amplifier is critical in achieving a high intercept passive mixer without degrading the noise floor of the system. this is a critical requirement in an interferer rich environment, such as cellular infrastructure, where blocking interferers can limit mixer performance. blocking dynamic range can benefit from a higher level of lo drive, which pushes the lo amplifier stages harder into compression and causes them to switch harder and to limit the small signal gain of the chain. both of these conditions are beneficial to low noise figure under blocking. nf under blocking can be improved several decibels for lo input power levels above 0 dbm. the lo amplifier topology inherently minimizes the dc current based on the lo operating voltage and the lo operating frequency. it is permissible to reduce the lo supply voltage down as low as 3.6 v, which drops the dc current rapidly. the mixer dynamic range varies accordingly with the lo supply voltage. no external biasing resistor is required for optimizing the lo amplifier. in addition, the adl5812 has a power-down mode. this power- down mode can be used with any supply voltage applied to the part. all of the spi inputs are designed to work with any logic family that provides a logic 0 input level of less than 0.4 v and a logic 1 input level that exceeds 1.4 v. all pins, including the rf pins, are esd protected and have been tested up to a level of 2000 v hbm and 1250 v cdm.
adl5812 rev. 0 | page 22 of 28 applications information basic connections the adl5812 mixer is designed to downconvert radio frequencies (rf) primarily between 700 mhz and 2800 mhz to lower intermediate frequencies (if) between 30 mhz and 450 mhz. figure 60 depicts the basic connections of the mixer. it is recommended to ac couple rf and lo input ports to prevent nonzero dc voltages from damaging the rf balun or lo input circuit. a rfin capacitor value of 22 pf is recommended. if port the mixer differential if interface requires pull-up choke inductors to bias the open-collector outputs and to set the output match. the shunting impedance of the choke inductors used to couple dc current into the if amplifier should be selected to provide the desired output return loss. the real part of the output impedance is approximately 200 , as seen in figure 31 , which matches many commonly used saw filters without the need for a transformer. this results in a voltage conversion gain that is approximately 6 db higher than the power conversion gain. when a 50 output impedance is needed, use a 4:1 impedance transformer, as shown in figure 60 . bias resistor selection external resistors, r1 and r2, are used to adjust the bias current of the integrated amplifier at the if terminal. it is necessary to have a sufficient amount of current to bias both the internal if amplifier to optimize dc current vs. optimum input ip3 performance. figure 42 and figure 43 provide the reference for the bias resistor selection when lower power consumption is considered at the expense of conversion gain and input ip3 performance. vcc red blk vpos agnd c25 22pf c24 22pf rfin2 c17 22pf rfin2 c6 22pf rfin1 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 21 1 11 pad vcc vcc vcc vcc c3 120pf c4 120pf c2 0.1f c13 10pf vcc c14 10pf c12 10pf c11 10pf c5 120pf c8 0.1f c7 22pf c2.3 10pf 3 4 6 2 1 c1 0.1f ifon ifop r20 open r21 0 ? r1 910 ? t1 tc4-1w+ l1 470nh l2 470nh v cc vcc vcc vcc vcc c3 120pf c4 120pf c27 0.1f c20 10pf c19 10pf c18 10pf c16 22pf c15 10pf c30 120pf 3 4 6 2 1 c26 0.1f ifon ifop r23 open r22 0 ? r2 910? t1 tc4-1w+ l3 470nh l4 470nh rf1 vpif1 vpif2 rfct1 nc nc nc nc nc nc rfct2 rf2 v1lo1 nc nc nc loip loin le data clk le data clk v2lo1 ifgm1 nc ifop1 ifon1 nc ifgd1 v1lo4 v1lo3 v1lo2 ifgm2 nc ifop2 ifon2 nc ifgd2 v2lo4 v2lo3 v2lo2 adl5812 09913-070 12 13 14 15 16 17 18 19 20 2 3 4 5 6 7 8 9 10 figure 60. evaluation board schematic
adl5812 rev. 0 | page 23 of 28 vgs programming the adl5812 allows programmability for internal gate-to-source voltages for optimizing mixer performance over the desired frequency bands. the adl5812 defaults the vgs setting to 0. both channels of the adl5812 are programmed together using the same vgs setting. power conversion gain, input ip3, nf, and input p1db can be optimized, as shown in figure 39 and figure 40 . low-pass filter programming the adl5812 allows programmability for the low-pass filter terminating the mixer output. this filter helps to block sum term mixing products at the expense of some noise figure and gain and can significantly increase input ip3. the adl5812 defaults the lpf setting to 0. both channels of the adl5812 are programmed together using the same lpf settings. power conversion gain, input ip3, nf, and input p1db can be optimized, as shown in figure 49 to figure 52 . rf balun programming the adl5812 allows programmability for the rf balun by allowing capacitance to be switched into both the input and the output, which allows the balun to be tuned to cover the entire frequency band (700 mhz to 2800 mhz). under most circum- stances, the input and output can be tuned together though sometimes it may be advantageous for matching reasons to tune them separately. the adl5812 defaults the rfb setting to 0. both channels of the adl5812 are programmed together using the same rfb settings. power conversion gain, input ip3, nf, and input p1db can be optimized, as shown in figure 45 and figure 48 .
adl5812 rev. 0 | page 24 of 28 register structure figure 61 illustrates the register map of the adl5812 . the adl5812 uses only register 5. because of this, set all of the control bits to five. when set to 0, the main enb and div enb bits, db7 and db6, respectively, enable the part. by setting one of these bits to 1, its channel is powered down. either channel can be powered down independently of the other. the rfb in cap dac and rfb out cap dac bits are used to tune the rf balun. in most cases, they are tuned together with the higher settings, 7, tuning for the low frequencies, and with the lower settings, 0, tuning for the high frequencies. there are times where it becomes advantageous to tune the input and output of the rf balun separately and that ability is provided. the lpf bits control the low-pass filter settings at the if output. the ability to tune the low-pass filter allows some trade-off between gain, noise figure, and input ip3 with higher settings, 3, providing higher input ip3 at the cost of some gain and noise figure and lower settings, 0, providing higher gain and lower nf at the cost of lower input ip3. the vgs bits control the vgs settings of the mixer core and allow further tuning of the device. table 11 lists the optimum settings characterized for each frequency band. all register bits default to 0. main enb div enb db23 db22 db21 db20 db19 db18 db17 db16 db15 db14 db13 db12 db11 db10 db9 db8 db7 db6 db5 db4 db3 db2 db1 db0 0 0 vgs2 vgs1 vgs0 lpf1 lpf0 0 cdo2 dcdo1 cdo0 0 cdi2 cdi1 cdi0 0 men den 0 0 0 c3(1) c2(0) c1(1) reserved control bits vgs lpf rfb out cap dac rfb in cap dac reserved den diversity enable 0 device enabled 1 device disabled men main enable 0 device enabled 1 device disabled cdo2 cdo1 cdo0 rf balun output tuning 000 0 ''' ' 111 7 cdi2 cdi1 cdi0 rf balun intput tuning 000 0 ''' ' 111 7 lpf1 lpf0 low pass filter setting 00 0 '' ' 11 3 vgs2 vgs1 vgs0 vgs setting 000 0 ''' ' 111 7 09913-024 figure 61. adl5812 register maps table 11. optimum settings rf frequency (mhz) lo frequency (mhz) vgs lpf rfb out cap dac rfb in cap dac 700 497 3 3 7 7 800 597 3 2 7 7 900 697 3 2 4 4 1000 797 3 2 3 3 1100 897 3 3 7 7 1200 997 3 3 7 7 1300 1097 3 3 7 7 1400 1197 3 3 7 7 1500 1297 3 3 5 5 1600 1397 3 3 6 6 1700 1497 3 3 5 5 1800 1597 3 3 5 5 1900 1697 3 3 5 5 2000 1797 3 3 4 4 2100 1897 3 3 4 4 2200 1997 3 3 3 3 2300 2097 3 1 3 3 2400 2197 3 1 3 3 2500 2297 3 3 2 2 2600 2397 3 1 2 2 2700 2497 3 1 2 2 2800 2597 3 2 1 1
adl5812 rev. 0 | page 25 of 28 evaluation board an evaluation board is available for the adl5812 . the standard evaluation board schematic is presented in figure 62 . the usb interface circuitry schematic is presented in figure 65 . the evaluation board layout is shown in figure 63 and figure 64 . the evaluation board is fabricated using rogers? 3003 material. table 12 details the configuration for the mixer characterization. the evaluation board software is available on www.analog.com . vcc red blk vpos agnd c25 22pf c24 22pf rfin2 c17 22pf rfin2 c6 22pf rfin1 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 21 1 11 pad vcc vcc vcc vcc c3 120pf c4 120pf c2 0.1f c13 10pf vcc c14 10pf c12 10pf c11 10pf c5 120pf c8 0.1f c7 22pf c2.3 10pf 3 4 6 2 1 c1 0.1f ifon ifop r20 open r21 0 ? r1 910? t1 tc4-1w+ l1 470nh l2 470nh vcc vcc vcc vcc vcc c3 120pf c4 120pf c27 0.1f c20 10pf c19 10pf c18 10pf c16 22pf c15 10pf c30 120pf 3 4 6 2 1 c26 0.1f ifon ifop r23 open r22 0 ? r2 910? t1 tc4-1w+ l3 470nh l4 470nh rf1 vpif1 vpif2 rfct1 nc nc nc nc nc nc rfct2 rf2 v1lo1 nc nc nc loip loin le data clk le data clk v2lo1 ifgm1 nc ifop1 ifon1 nc ifgd1 v1lo4 v1lo3 v1lo2 ifgm2 nc ifop2 ifon2 nc ifgd2 v2lo4 v2lo3 v2lo2 adl5812 09913-072 12 13 14 15 16 17 18 19 20 2 3 4 5 6 7 8 9 10 figure 62. evaluation board schematic table 12. evaluation board configuration components description default conditions c1, c2, c8, c11, c12, c13, c14, c15, c18, c19, c20, c23, c26, c27 power supply decoupling. nominal supply decoupling consists of a 0.1 f capacitor to ground in parallel with a 10 pf capacitor to ground positioned as close to the device as possible. c1, c2, c26, c27 = 0.1 f (size 0402), c8, c11, c12, c13, c14, c15, c18, c19, c20, c23 = 10 pf (size 0402) c6, c7, c24, c25 rf input interface. the input chan nels are ac-coupled through c6 and c24. c7 and c25 provide bypassing fo r the center tap of the rf input baluns. c6, c24 = 22 pf (size 0402), c7, c25 = 22 pf (size 0402) c3, c4, c5, c28, c29, c30, l1, l2, l3, l4, r20, r21, r22, r23, t1, t2 if output interface. the open-collecto r if output interfaces are biased through pull-up choke inductors l1, l2, l3, and l4. t1 and t2 are 4:1 impedance transformers used to provide single-ended if output interfaces, with c5 and c30 providing center-tap bypassing. remove r21 and r22 for balanced output operation. c3, c4, c5, c28, c29, c30 = 120 pf (size 0402), l1, l2, l3, l4 = 470 nh (size 0603), r20, r23 = open, r21, r22 = 0 (size 0402), t1, t2 = tc4-1w+ (mini-circuits?) c17 lo interface. c17 provides ac coupling for the loip local oscillator input. c17 = 22 pf (size 0402) r1, r2 bias control. r1and r2 set the bias point for the internal if amplifier. r1, r2 = 910 (size 0402)
adl5812 rev. 0 | page 26 of 28 09913-068 figure 63. evaluation board top layer 0 9913-069 figure 64. evaluation board bottom layer decoupling for u6 330pf 330pf 330pf 5v_usb 897-43-005-00-100001 j6 g1 g2 g3 g4 1 2 3 4 5 22pf c40 24.000000mhz y 2 24 1 3 22pf c41 3v3_usb 3p3v c37 c36 c38 r9 r10 r7 r8 7 8 5 6 4 3 2 1 u7 c35 c34 c39 r13 r14 r12 r11 c49 r15 c50 r16 c51 r19 r18 r17 3 2 1 p1 4 5 44 55 43 32 27 17 11 16 15 42 14 2 1 52 51 50 49 48 47 46 45 25 24 23 22 21 20 19 18 pad 40 39 38 37 36 35 34 33 13 56 53 41 28 26 12 8 9 31 30 29 54 7 3 10 6 u6 6 pad 2 1 8 7 5 3 u5 1 1 dgnd r5 r6 c48 c46 c47 c44 c45 c42 c43 a c d1 r3 c31 r4 c32 c33 dni dni blk org 140k 24lc64-i-sn 3v3_usb 10pf 3v3_usb 0.1uf 3v3_usb cy7c68013a-56ltxc 3v3_usb dni tbd0402 3v3_usb 1.0uf clk data le 2k 2k 0.1uf 0.1uf 100k 100k 10pf 0 1k dni 0 0 1k dni tbd0402 dni 1k dni tbd0402 dni 0 0 0 samtectsw10608gs3pin 0.1uf 0.1uf 0.1uf 0.1uf 0.1uf 0.1uf 0.1uf 1000pf 78.7k adp3334acpz 1.0uf 2k sml-210mtt86 0 5v_usb 0.1uf dgnd dgnd dgnd dgnd dgnd dgnd agnd dgnd dgnd dgnd dgnd dgnd dgnd gnd scl sda wc_n a2 a1 a0 vcc dgnd dgnd dgnd case dgnd dgnd pins gnd dgnd dgnd dgnd dgnd dgnd dgnd pad clkout pd7_fd15 pd6_fd14 pd5_fd13 pd4_fd12 pd3_fd11 pd2_fd10 pd1_fd9 pd0_fd8 wakeup reset_n pa7_flagd_slcs_n pa6_pktend pa5_fifoadr1 pa4_fifoadr0 pa3_wu2 pa2_sloe pa1_int1_n pa0_int0_n vcc ctl2_flagc ctl1_flagb ctl0_flaga gnd pb7_fd7 pb6_fd6 pb5_fd5 pb4_fd4 pb3_fd3 pb2_fd2 pb1_fd1 pb0_fd0 sda scl reserved ifclk dminus dplus agnd xtalin xtalout avcc rdy1_slwr rdy0_slrd in1 in2 out2 out1 pad fb gnd sd_n dgnd dgnd 09913-071 figure 65. usb interface circuitry on the evaluation board
adl5812 rev. 0 | page 27 of 28 outline dimensions 0.45 0.40 0.35 * compliant to jedec standards mo-208 except for exposed pad dimension 1 top view bottom view pin 1 index area 6.00 bsc sq 40 11 20 21 30 31 10 exposed pad p i n 1 i n d i c a t o r * 4.19 4.14 sq 4.09 0.30 0.25 0.20 0.58 0.53 0.48 seating plane 0.90 0.85 0.80 0.21 max 0.19 min 0.02 ref 0.50 bsc for proper connection of the exposed pad, refer to the pin configuration and function descriptions section of this data sheet. 04-24-2008-a figure 66. 40-lead lead frame chip scale package [lfcsp_vq] 6 mm 6 mm body, very thin quad (cp-40-6) dimensions shown in millimeters ordering guide model 1 temperature range package description package option quantity adl5812acpz-r7 ?40c to +85c 40-lead lead frame chip scale package [lfcsp_vq] cp-40-6 750 ADL5812-EVALZ evaluation board 1 z = rohs compliant part.
adl5812 rev. 0 | page 28 of 28 notes ?2011 analog devices, inc. all rights reserved. trademarks and registered trademarks are the prop erty of their respective owners. d09913-0-7/11(0)

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